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| MC10E160, MC100E160 5V ECL 12-Bit Parity Generator/Checker The MC10E/100E160 is a 12-bit parity generator/checker. The Q output is HIGH when an odd number of inputs are HIGH. A HIGH on the Enable input (EN) forces the Q output LOW. The 100 Series contains temperature compensation. http://onsemi.com MARKING DIAGRAMS 1 28 * * * * * * * * Provides Odd-HIGH Parity of 12 Inputs Shiftable Output Register with Hold 900 ps Max. D to Q/Q Output Enable Asynchronous Register Reset Dual Clocks PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V Internal Input to 50 KW Pulldown Resistors Machine Model; > 7 V Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test PLCC-28 FN SUFFIX CASE 776 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week MC10E160FN AWLYYWW 1 28 * * ESD Protection: Human Body Model; > 1 KV, * * Moisture Sensitivity Level 1 * * MC100E160FN AWLYYWW For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V-0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 312 devices ORDERING INFORMATION Device MC10E160FN MC10E160FNR2 MC100E160FN MC100E160FNR2 Package PLCC-28 PLCC-28 PLCC-28 PLCC-28 Shipping 37 Units/Rail 500 Units/Reel 37 Units/Rail 500 Units/Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. (c) Semiconductor Components Industries, LLC, 2006 June, 2006 - Rev. 6 1 Publication Order Number: MC10E160/D MC10E160, MC100E160 LOGIC DIAGRAM AND PINOUT ASSIGNMENT D4 25 D5 D6 D7 VEE D8 D9 D10 26 27 28 1 D3 24 D2 23 D1 22 D0 21 EN VCCO 20 19 18 17 16 Q Q VCC Y Y VCCO NC PIN DESCRIPTION PIN D0 - D11 S-IN EN HOLD SHIFT CLK1, CLK2 R Q, Q Y, Y VCC, VCCO VEE NC FUNCTION ECL Data Inputs ECL Serial Data Input ECL Enable, active LOW ECL Hold, active LOW ECL Shift, active HIGH ECL Clock Inputs ECL Reset Inputs ECL Direct Output ECL Register Output Positive Supply Negative Supply No Connect Pinout: 28-Lead PLCC (Top View) 15 14 13 12 2 3 4 5 6 7 8 9 10 11 D11 HOLD S-IN SHIFT CLK1 CLK2 R * All VCC and VCCO pins are tied together on the die. Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 EN HOLD S-IN SHIFT CLK1 CLK2 R LOGIC DIAGRAM Q 0 MUX 1 SEL 0 MUX 1 SEL D R Y Y http://onsemi.com 2 MC10E160, MC100E160 MAXIMUM RATINGS (Note 1) Symbol VCC VI Iout TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 LFPM 500 LFPM Standard Board <2 to 3 sec @ 248C 28 PLCC 28 PLCC 28 PLCC Condition 1 VEE = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 8 6 -6 50 100 0 to +85 -65 to +150 63.5 43.5 22 to 26 265 Unit V V V mA mA C C C/W C/W C/W C 1. Maximum Ratings are those values beyond which device damage may occur. 10E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 2) 0C Symbol IEE VOH VOL VIH VIL IIH Characteristic Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage Input LOW Voltage Input HIGH Current CLK1, CLK2 R All Other Inputs Input LOW Current 0.5 0.3 200 300 150 0.5 0.25 200 300 150 0.3 0.2 200 300 150 mA mA mA mA 3980 3050 3830 3050 Min Typ 82 4070 3210 3995 3285 Max 98 4160 3370 4160 3520 4020 3050 3870 3050 Min 25C Typ 82 4105 3210 4030 3285 Max 98 4190 3370 4190 3520 4090 3050 3940 3050 Min 85C Typ 82 4185 3227 4110 3302 Max 98 4280 3405 4280 3555 Unit mA mV mV mV mV IIL NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. 2. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.06 V. 3. Outputs are terminated through a 50 ohm resistor to VCC - 2 volts. 100E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= -5.0 V (Note 8) 0C Symbol IEE VOH VOL VIH VIL IIH Characteristic Power Supply Current Output HIGH Voltage (Note 5) Output LOW Voltage (Note 5) Input HIGH Voltage Input LOW Voltage Input HIGH Current CLK1, CLK2 R All Other Inputs Input LOW Current 0.5 0.3 200 300 150 0.5 0.065 200 300 150 0.3 0.2 200 300 150 mA mA mA mA -1020 -1950 -1170 -1950 Min Typ 82 -930 -1790 -1005 -1715 Max 98 -840 -1630 -840 -1480 -980 -1950 -1130 -1950 Min 25C Typ 82 -895 -1790 -970 -1715 Max 98 -810 -1630 -810 -1480 -910 -1950 -1060 -1950 Min 85C Typ 82 -815 -1773 -890 -1698 Max 98 -720 -1595 -720 -1445 Unit mA mV mV mV mV IIL NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. 4. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.06 V. 5. Outputs are terminated through a 50 ohm resistor to VCC - 2 volts. http://onsemi.com 3 MC10E160, MC100E160 100E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 6) 0C Symbol IEE VOH VOL VIH VIL IIH Characteristic Power Supply Current Output HIGH Voltage (Note 7) Output LOW Voltage (Note 7) Input HIGH Voltage Input LOW Voltage Input HIGH Current CLK1, CLK2 R All Other Inputs IIL NOTE: Input LOW Current 0.5 0.3 200 300 150 0.5 0.25 200 300 150 0.5 0.2 200 300 150 mA mA mA mA 3975 3190 3835 3190 Min Typ 82 4050 3295 3975 3355 Max 98 4120 3380 4120 3525 3975 3190 3835 3190 Min 25C Typ 82 4050 3255 3975 3355 Max 98 4120 3380 4120 3525 3975 3190 3835 3190 Min 85C Typ 94 4050 3260 3975 3355 Max 113 4120 3380 4120 3525 Unit mA mV mV mV mV Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.8 V. 7. Outputs are terminated through a 50 ohm resistor to VCC - 2 volts. 100E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= -5.0 V (Note 8) 0C Symbol IEE VOH VOL VIH VIL IIH Characteristic Power Supply Current Output HIGH Voltage (Note 9) Output LOW Voltage (Note 9) Input HIGH Voltage Input LOW Voltage Input HIGH Current CLK1, CLK2 R All Other Inputs IIL NOTE: Input LOW Current 0.5 0.3 200 300 150 0.5 0.25 200 300 150 0.5 0.2 200 300 150 mA mA mA mA -1025 -1810 -1165 -1810 Min Typ 82 -950 -1705 -1025 -1645 Max 98 -880 -1620 -880 -1475 -1025 -1810 -1165 -1810 Min 25C Typ 82 -950 -1745 -1025 -1645 Max 98 -880 -1620 -880 -1475 -1025 -1810 -1165 -1810 Min 85C Typ 94 -950 -1740 -1025 -1645 Max 113 -880 -1620 -880 -1475 Unit mA mV mV mV mV Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. 8. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.8 V. 9. Outputs are terminated through a 50 ohm resistor to VCC - 2 volts. http://onsemi.com 4 MC10E160, MC100E160 AC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V or VCCx= 0.0 V; VEE= -5.0 V (Note 10) 0C Symbol fMAX tPLH tPHL Characteristic Maximum Toggle Frequency Propagation Delay to Output D to Q En to Q CLK to Y R to Y ts Setup Time D HOLD S-IN SHIFT th Hold Time D HOLD S-IN SHIFT tJITTER tr tf NOTE: Random Clock Jitter (RMS) Rise/Fall Time (20 - 80%) 300 450 650 300 450 650 300 450 650 - 400 100 300 200 - 900 - 300 -150 - 250 <1 - 400 100 300 200 - 900 - 300 -150 - 250 <1 - 400 100 300 200 - 900 - 300 -150 - 250 <1 ps ps 1200 600 350 500 900 300 150 250 1200 600 350 500 900 300 150 250 1200 600 350 500 900 300 150 250 ps 400 300 275 275 650 550 500 500 950 750 700 725 400 300 275 275 650 550 500 500 950 750 700 725 400 300 275 275 650 550 500 500 950 750 700 725 ps Min 700 Typ 1100 Max Min 700 25C Typ 1100 Max Min 700 85C Typ 1100 Max Unit MHz ps Devices are designed to meet the AC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained. 10. 10 Series: VEE can vary -0.46 V / +0.06 V. 100 Series: VEE can vary -0.46 V / +0.8 V. http://onsemi.com 5 MC10E160, MC100E160 Q Driver Device Q 50 W 50 W D D Receiver Device V TT VTT = VCC - 2.0 V Figure 1. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1404 AN1405 AN1406 AN1503 AN1504 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020 - - - - - - - - - - - - ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) ECLinPS I/O SPICE Modeling Kit Metastability and the ECLinPS Family Interfacing Between LVDS and ECL ECLinPS Lite Translator ELT Family SPICE I/O Model Kit Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes Termination of ECL Logic Devices http://onsemi.com 6 MC10E160, MC100E160 PACKAGE DIMENSIONS PLCC-28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE E B U 0.007 (0.180) M T L -M M S N S S -N- Y BRK D 0.007 (0.180) T L -M N S -L- -M- Z W V D X VIEW D-D G1 0.010 (0.250) S T L -M S N S 28 1 A 0.007 (0.180) M M T L -M T L -M S S N N S S Z H 0.007 (0.180) M T L -M S N S R 0.007 (0.180) C G G1 0.010 (0.250) E 0.004 (0.100) K1 J -T- SEATING PLANE K F VIEW S 0.007 (0.180) VIEW S M T L -M S N S S T L -M S N S NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 0.025 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 0.020 2 10 0.410 0.430 0.040 MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.79 2.29 0.33 0.48 1.27 BSC 0.81 0.66 0.51 0.64 11.58 11.43 11.58 11.43 1.07 1.21 1.07 1.21 1.42 1.07 0.50 2 10 10.42 10.92 1.02 http://onsemi.com 7 MC10E160, MC100E160 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 8 MC10E160/D |
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